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YGV629
VC1
Video Controller 1 Outline
YGV629 (Function name: VC1, hereinafter described as VC1) is a VDP (Video Display Processor), which has a pattern rendering function by the sprite method according to the attribute settings and a direct line rendering function. Since various effect functions are included sufficiently in the sprite function and line rendering function, more effective presentation can be realized. Since VC1 can display the bit map image with free display resolution, NTSC to SVGA, on any screen size of monitor, OSD display control for various display units can be made. And, VC1 includes a line buffer as a VRAM, so the system can be built with a little part. In addition, pattern memory can be connected directly, so that the amount of the control program can be reduced.
Features
Display Function Pattern rendering by the sprite method according to the attribute settings, and OSD display by the direct line rendering according to the attribute settings. Two display layers: Sprite display layer and Line display layer, up to 341 can be displayed. However, for the line display layer, up to 1 layer can be displayed. Alpha-blending function between layers. Sprite Plane Function Sprite display of the field on the screen, up to 341 Size 8x8 to 512x512 dots, independent selection (horizontal & vertical) possible. (in 8 dots) 2, 16, 32, 64, or 256 palette colors in 64k colors, 64k-color natural picture display by 16-bit RGB Reverse function in right to left or up and down Scaling function Alpha-blending function in pixels Anti-aliasing function at the outline part
YGV629 CATALOG CATALOG No.: LSI-4GV629A50 2006.05
YGV629
Line Rendering Function Line display of the field, up to 510 Displayable color: 32768 colors (RGB555) or palette index (10-bit) designation Line width: 1 dot to 16 dots available (in dots) Anti-alias rendering available Display Resolution Display monitor interface timing generation for NTSC, PAL, QVGA, Wide QVGA, VGA, Wide VGA, and SVGA Example of the supported resolution: 320x240, 400x240, 640x480, 800x480, 800x600, etc. External Synchronizing Function External Memory Pattern memory up to 256M bits Mask ROMi, SRAM, and NOR type flash-memory connection Access timing settings by the period of the system clock Bus width 8-bit/16-bit selection Others 8-bit parallel interface and serial interface supported Indirect mapping to the built-in register and table through the access port. Analog RGB output and Digital RGB data output, with 6 bits DAC for each R,G, and B 144 pin plastic LQFP, pin lead plating is Pb-free. (YGV629-VZ) CMOS, 3.3V single power supply
i
Timing-compatible ROM (OTPROM, EPROM, etc.) also can be connected.
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Block Diagram
Pattern Memory I/F Monitor I/F
Sprite Rendering Pattern Memory Interface Processor Line Buffer F
Frame Data Controller DAC
R, G, B IREF DR5-0 DG5-0 DB5-0 HCSYNC_N VSYNC_N
MD[15:0] MA[24:0] MOE_N MWE_N RAHZ_N
DAC
Sprite Plane Generator
DAC
CRTC
CPU I/F D[7:0] PS[2:0] CS_N RD_N WR_N WAIT_N READY_N INT_N SDIN SCLK SRI_N RESET_N
BLANK_N DOTCLK FSC YS_N HSIN_N VSIN_N
Color Palette
General Table
Registers To all blocks Clock
Clock
CPU Interface
Line Plane Generator
Gen.
XIN XOUT FILTER DTCKIN PLLCTL[5:0]]
Line Rendering Processor
Examples of System Composition
3 PS2-0 D7-0 MA24-0 MD15-0 MOE_N MWE_N 25 16
Pattern Memory
max 256Mbit
CPU
8
VC1
XIN
CSYNC_N XOUT R,G,B 3
LCD Monitor
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Stand-alone system
Pattern ROM
RAM
ROM VC1
X'tal Digital RGB
CPU
Analog RGB
OSD to the Analog Image
Pattern ROM
RAM
ROM VC1
X'tal Hsync,Vsync Analog Image +OSD YS_N
CPU
Analog RGB
Analog Image
Analog Switch
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Pin Table
Pin Name No. I/O CPU Interface D7-0 8 I/O PS2-0 3 I CS_N 1 I RD_N 1 I WR_N 1 I WAIT_N 1 OT READY_N 1 OT INT_N 1 Od SER_N 1 I SCS_N 1 I SDIN 1 I SDOUT 1 OT SCLK 1 I RESET_N 1 I Pattern Memory Interface MD15-0 16 I/O MA24-0 25 OT MOE_N 1 OT MWE_N 1 OT RAHZ_N 1 I Monitor Interface R,G,B 3 O IREF 1 DR5-0 6 O DG5-0 6 O DB5-0 6 O VSYNC_N 1 O HCSYNC_N 1 O I I O O O O I O I I I Function CPU Data Bus CPU Port Selection Chip Select Read Pulse Write Pulse CPU Bus Wait CPU Bus Ready Interrupt CPU Interface Selection Serial Interface Chip Select Serial Interface Data Input Serial Interface Data Output Serial Clock Input Reset Pattern Memory Data Bus Pattern Memory Address Bus Pattern Memory Output Enable Pattern Memory Write Pulse Pattern Memory High Impedance Switching Analog Image Output DAC Reference Power Supply Digital Image R Output Digital Image G Output Digital Image B Output Vertical Synchronizing Signal Output Horizontal Synchronizing / Composite Synchronizing Signal Output Vertical Synchronizing Input Horizontal Synchronizing Input Display Timing Output Sub-carrier Clock YS Output Dot Clock Output Reference Clock Input X'tal connection pin Display system Clock Input Display system Clock Selection PLL Filter Connection PLL Control OT: 3-state output, 5Tr: 5V Tolerant, Level LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Analog Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS 4mA 4mA 4mA 4mA 5Tr Drive 4mA
4mA 4mA 4mA
4mA
4mA 4mA 4mA 4mA
4mA 4mA 4mA 4mA 4mA
VSIN_N 1 HSIN_N 1 BLANK_N 1 FSC 1 YS_N 1 DOTCLK 1 Clock XIN 1 XOUT 1 DTCKIN 1 DTCKS_N 1 FILTER 1 PLLCTL5-0 6 Od: open drain output,
LVCMOS LVCMOS Analog LVCMOS Drive: driving capability

Note) VC1 has no built-in pull up resistor. Pull up the pins externally as necessary. The tolerant attribute is an attribute of the input buffer, output buffer that can become the high-impedance state, and bi-directional buffer, and indicates it can endure the 5V signal.
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Pin Name No. I/O Function Level Power Supply VDD 11 - Digital Power Supply VSS 14 - Digital VSS PLLVDD 1 - Power Supply for PLL PLLVSS 1 - VSS for PLL AVDD 1 - Power Supply for DAC AVSS 1 - VSS for DAC LSI Test Pin XTEST2-0 3 I Test Pin LVCMOS Others NC 4 - No connection Pin. Connect nothing. Od: open drain output, OT: 3-state output, 5Tr: 5V Tolerant, Drive: driving capability Note) VC1 has no built-in pull up resistors. Pull up the pins externally as necessary. The tolerant attribute is an attribute of the input buffer, output buffer that can become the high-impedance state, and bi-directional buffer, and indicates it can endure the 5V signal. 5Tr Drive
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Pin Assignment Table
No
Pin Name
PLLVDD FILTER PLLVSS NC PLLCTL5 PLLCTL4 PLLCTL3 PLLCTL2 PLLCTL1 PLLCTL0 DTCKS_N DTCKIN VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 WAIT_N READY_N INT_N VDD VSS CS_N WR_N RD_N PS2 PS1 PS0 SDOUT SDIN SCS_N
I/O A
No 37 38 39 40 41 42 43 44
Pin Name
SCLK SER_N RESET_N VSS VDD MA0 MA1 MA2 MA3 MA4 MA5 VSS MA6 MA7 MA8 MA9 MA10 MA11 VDD VSS MA12 MA13 MA14 MA15 MA16 MA17 VSS MA18 MA19 MA20 MA21 MA22 MA23 MA24 VDD VSS
I/O I I I$
No 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Pin Name
MWE_N MOE_N MD15 MD7 MD14 MD6 MD13 MD5 VSS VDD MD12 MD4 MD11 MD3 MD10 MD2 MD9 MD1 VSS VDD MD8 MD0 RAHZ_N XTEST2 XTEST1 XTEST0 VSIN_N HSIN_N NC AVDD R G B IREF AVSS NC
I/O OT OT I/O I/O I/O I/O I/O I/O
No 109 110 111 112 113 114 115 116 117 118 119 121 122 123 124 125 126 127 128 129 130 131 132
Pin Name
VDD VSS DR0 DR1 DR2 DR3 DR4 DR5 VSS VDD DG0 DG2 DG3 DG4 DG5 VSS VDD DB0 DB1 DB2 DB3 DB4 DB5 VSS FSC YS_N VSYNC_N HCSYNC_N BLANK_N DOTCLK VDD XIN XOUT VSS NC
I/O
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
I I I I I I I I
45
46 47 48 49 50 51 52 53 54 55 56 57
OT OT OT OT OT OT OT OT OT OT OT OT
O O O O O O
I/O I/O I/O I/O I/O I/O I/O I/O
O O O O O O
120 DG1
I/O I/O I/O I/O I/O I/O I/O I/O OT OT Od
89
90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
58
59 60 61 62 63 64 65 66 67 68 69 70 71 72
OT OT OT OT OT OT OT OT OT OT OT OT OT
I I I I I I OT I I
I/O I/O I I I I I I
O O O O O O O O O O O O I O
133
134 135 136 137 138 139 140 141 142 143 144
AO AO AO A
NC indicates a no-connection pin. Make an open state electrically. The meaning of each symbol for I/O is as follows. I: Input, I$: Schmitt trigger input, I/O: Input Output, O: Output, Od: Open drain output, OT: 3-state output, AO: Analog output, A: Analog pin
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Pin Assignment
< Top View >
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Pins Functions
A 3.3V supply voltage is supplied to VC1. Therefore, the interface between peripheral circuits uses LVCMOS (3.3V) for input/output. However, input pins, input/output pins, tri-state output pins, and an open-drain pin except XIN, XOUT, and the analog pins can interface with the 5V TTL level compatible device because they have 5V voltage tolerance. Use the independent resistors for each pin, when pulling up or down the input pin and the input output pin externally. However, the common resistor can be used between the input pins when pulling up or down the input signal to the input pin. And, when pulling down the tolerant pin, connect to the ground level, through a resistor with 7k or lower.
Power Supply
VC1 needs a 3.3V single power supply. There is a dedicated analog power supply pin for the built-in PLL and DAC as well as the digital power supply pin. There is no restriction for the procedure to turn on the power supplies. Please power on or power off the power supplies so that the time difference from the first power supply to the last one becomes within 1 second. VDD (Power supply Pin No.14, 26, 41, 55, 71, 82, 92, 109, 118, 126, 140) VSS (Power supply Pin No.13, 27, 40, 48, 56, 63, 72, 81, 91, 110, 117, 125, 133, 143) Power supply pins for the internal digital circuit. Supply 3.3V to the VDD pin, and supply the ground level to the VSS pin. PLLVDD (Power supply Pin No.1) PLLVSS (Power supply Pin No.3) Analog Power supply pin for the built-in PLL Supply 3.3V to the PLLVDD pin, and supply the ground level to the PLLVSS pin. AVDD (Power supply Pin No.102) AVSS (Power supply Pin No.107) Analog Power supply pin for the built-in DAC
System Reset
VC1 must be reset in the power-on. RESET_N (Schmitt trigger input Pin No.39) Reset pin. Input the power-on-reset signal. The reset signal with the given time must be input after the power-on. The pin is low active. The pin uses a schmitt trigger type buffer.
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Clock
Supply two clocks of the display system clock and the reference clock to the VC1 separately. The display system clock becomes the original of a clock (dot clock) that is used for outputting monitor scan timing and display data. The reference clock becomes the original of a clock (system clock) that is used for the process except the above. The system clock and dot clock can be generated from the reference clock by supplying only the reference clock to VC1. XIN (Input Pin No.141) XOUT (Output Pin No.142) The reference clock input pin. Reference clock of the built-in PLL is input. DTCKIN (Input Pin No.12) Display system clock input pin. Input a clock which becomes the original of a clock (dot clock) that is used for outputting monitor scan timing and display data. DTCKS_N (Input Pin No.11) Display system clock selection pin. The signal selects a pin to input the display system clock. PLLCTL5-0 (Input Pin No.5-10) PLL control pin. The pins set the multiplication number of the system clock that is generated in the built-in PLL to the reference clock. FILTER (Analog Pin No.2) A filter connection pin for the built-in PLL that is used for the system clock oscillation.
CPU Interface
Each CPU interface pin is used for the interface with the host CPU. The host CPU can control VC1 as an external I/O device. The CPU interface of VC1 can select the 8-bit parallel interface or the serial interface. And, since its access timing is asynchronous interface, connection to various CPUs is possible. D7-0 (Input Output Pin No.15-22) CPU data bus pin. The data bus pins are connected to the CPU external bus when 8-bit parallel interface is selected. PS2-0 (Input Output Pin No.31-33) Selection pin for the internal port. Connect the pins to the CPU external address bus when 8-bit parallel interface is selected. CS_N (Input Pin No.28) Chip-select input pin. Input the chip-select signal to the pin when 8-bit parallel interface is selected. RD_N (Input Pin No.30) Read pulse input pin. The strobe signal for the data read (from CPU to VC1) is input when using in 8-bit parallel interface. WR_N (Input Pin No.29) Write pulse input pin. The strobe signal for the data write (from CPU to VC1) is input when using in 8-bit parallel interface.
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WAIT_N (3-state output Pin No.23) CPU bus wait pin. The bus wait request signal to CPU is output from this pin when using in 8-bit parallel interface. READY_N (3-state output Pin No.24) CPU bus ready pin. The bus ready signal to CPU is output from this pin when using in 8-bit parallel interface. INT_N (Open drain output Pin No.25) Interrupt signal output pin. An interrupt request signal to CPU is output. SER_N (Output Pin No.38) CPU interface selection pin. This pin selects which to select as a CPU interface from the serial interface or the 8-bit parallel interface. SCS_N(Input Pin No.36) Serial interface chip select input pin. The chip-select signal is input when using in the serial interface. SDIN pin and SCLK pin becomes valid SDIN (Input Pin No.35) Serial data input pin. Data is input when using in serial interface. SDOUT (3-state output Pin No.34) Serial data output pin. Data is output when using in serial interface. SCLK (Input Pin No.37) Serial clock input pin. A clock is input when using in serial interface.
Pattern Memory Interface
Each pin of the pattern memory interface is used as the interface with the pattern memory, which is connected to the VC1 local bus. Mask-ROM, NOR type flash-memory, and SRAM, etc. can be connected to the pattern memory. MD15-0 (Input Output Pin No.75-80, 83-90, 93, 94) Pattern memory data bus pin. These pins are connected to the data bus of the pattern memory. MA24 - 0(3-state output Pin No.42-47, 49-54, 57-62, 64-70) Pattern memory address bus pin. These pins are connected to the address bus of the pattern memory. MOE_N(3-state output Pin No.74) Pattern memory output enable pin. The output enable signal to the pattern memory is output. MWE_N(3-state output Pin No.73) Pattern memory write pulse output pin. The write enable signal to the pattern memory is output. RAHZ_N (Input Pin No.95) Pattern memory high-impedance switching pin.
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Monitor Interface Each pin of the monitor interface is used for the interface with the external monitor. Since the display data is output in both of analog and digital signal, use them according to the specification of the external monitor interface. R (Analog output Pin No.103) G (Analog output Pin No.104) B (Analog output Pin No.105) Analog RGB output pin. Analog signals: R, G, and B of the display data is output. IREF (Analog Pin No.106) A pin for the DAC reference power supply. The reference current for DAC is input. DR5-0 (Output PinNo.111-116) DG5-0 (Output PinNo.119-124) DB5-0 (Output PinNo.127-132) Digital RGB output pin. VSYNC_N (Output Pin No.136) Vertical synchronizing signal output pin. The vertical synchronizing signal is output in synchronization with DOTCLK. HCSYNC_N (Output Pin No.137) Horizontal synchronizing signal / composite synchronizing signal output pin. The horizontal synchronizing signal or composite synchronizing signal is output in synchronization with DOTCLK. VSIN_N (Input Pin No.99) Vertical synchronizing signal input pin. The external vertical sync for the reset of the internal vertical counter is input. HSIN_N (Input Pin No.100) Horizontal synchronizing signal input pin. The external horizontal sync for the reset of the internal horizontal counter is input. BLANK_N (Output Pin No.138) Display timing output pin. A signal that indicates the blank interval is output in synchronization with DOTCLK. FSC (Output Pin No.134) Sub-carrier clock output pin. The sub-carrier clock, which is used in the video encoder is output. YS_N (Output Pin No.135) YS signal output pin. YS signal is output in synchronization with DOTCLK when superimpose is performed. DOTCLK (Output Pin No.139) Dot clock output pin. Dot clock is output from this pin.
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LSI Test For each pin for the LSI test, be sure to observe the way of signal input, which is regulated here strictly. XTEST2-0 (Input Pin No.96-98) Teat mode setting pin for VC1 test. Be sure to use under the following settings. Pin Name XTEST2 XTEST1 XTEST0 Input Level H H H
Others NC (Pin No.4, 101, 108, 144) Non connection pin. Nothing is connected.
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Electrical Characteristics
Absolute Maximum Ratings Items Symbol Power Supply (VDD pin) VDD DAC Power Supply (AVDD pin) AVDD PLL Power Supply (PLLVDD pin) PLLVDD Input Pin Voltage (5V tolerant pin) VI Input Pin Voltage (Except the above) VI Output Pin Voltage (Including the 5V tolerant pin and the input VO Output pin) Output Pin Voltage (Except the above) VO Input Pin Current II Output Pin Current IO Storage Temperature Tstg Note1) A value based on the reference of VSS(GND)=0V. Recommended Operating Condition Items Symbol Power Supply (VDD pin) VDD DAC Power Supply (AVDD pin) AVDD PLL Power Supply (PLLVDD pin) PLLVDD Operating Ambient Temperature TOP Note1) A value based on the reference of VSS(GND)=0V. Rating -0.5 to +4.6 -0.5 to +4.6 -0.5 to +4.6 -0.5 to +5.5 -0.5 to VDD+0.5(4.6 Max.) -0.5 to +5.5 -0.5 to VDD+0.5(4.6 Max.) -20 to +20 -20 to +20 -50 to +125 Unit Note V 1 V 1 V 1 V 1 V 1 V V mA mA C 1 1
Min. 3.0 3.0 3.0 -40
Typ. 3.3 3.3 3.3
Max. 3.6 3.6 3.6 +85
Unit Note V 1 V 1 V 1 C
Consumption Current Items Conditions Symbol Min. Typ. Max. Unit Note 1 Total Power Consumption PD 1023 mW Consumption Current CL=20pF VIL=GND 1 VDD IVDD 200 mA VIH=VDD 1 PLLVDD IPVD 4 mA 1 IAVD AVDD 80 mA Note1) Consumption Current value and Power consumption value are the values under the recommended operating condition.
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DC Characteristics Items Symbol Low level Input Voltage (XIN pin) VIL Low level Input Voltage (Except XIN pin) VIL High level Input Voltage (XIN pin) VIH High level Input Voltage (Except XIN pin) VIH Built-in DAC recommended operating condition Power Supply Voltage (AVDx pin) Reference Current (IREF pin) Output Load (R,G,B) Note1) A value based on the reference of VSS(GND)=0V Min. -0.3 -0.3 VDDx0.7 2.0 Typ. Max. VDDx0.3 0.8 VDD+0.3 5.5 Unit V V V V Note 1 1 1 1
3.0
3.3 -9.38 37.5
3.6
V mA
1
Conditions Symbol Min. Typ. IOL=100A 0 VOL Low level Output Voltage (Except XOUT pin) IOL=2mA 0 VOL IOH= -100A VOH VDD-0.2 High level Output Voltage (Except XOUT pin) IOH= -2mA 2.4 VOH Input leak Current ILI -10 Output leak Current ILO -25 Note1) A value based on the reference of VSS(GND)=0V
Items
Max. 0.2 0.4 VDD VDD +10 +25
Unit V V V V A A
Note 1 1 1 1
Items Input Pin Capacitance Output Pin Capacitance Input Output Pin Capacitance
Symbol CI CO CIO
Min.
Typ.
Max. 10 10 10
Unit pF pF pF
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AC Characteristics Measurement Conditions Input Voltage: 0V to VDD Input Transition Time: 1ns (Transition time is regulated between VDDx0.2 and VDDx0.8) Measurement Reference Voltage: Input VIL or VIH Output VDDx0.5 [V] Output Load Capacitance: 20pF Clock Input No. Items Symbol Min. Typ. Max. Unit Note XIN Input Clock Frequency fXIN 6 40 MHz 1 XIN Clock Cycle Time tXIN 25 166 ns DTCKIN Input Clock Frequency fDTCKIN 40 MHz 2 DTCKIN Clock Cycle Time tDTCKIN 25 ns 3 XIN, DTCKIN Clock High Level Pulse Width twhCLK 7.5 ns 4 XIN, DTCKIN Clock Low Level Pulse Width twlCLK 7.5 ns 5 SYCLK(PLL Out) Clock Cycle Time tSYCLK 12.5 16.6 ns 1 6 DCLK Clock Cycle Time tDCLK 25 ns 2 Note1) SYCLK is an internal clock generated in the PLL. tSYCLK is a regulation to the value that is found by the following formula, to the input clock to XIN pin. tSYCLK = tXIN x k / n (1 k 4, 1 n 16) Note2) DCLK is a Dot Clock that is used inside.
1, 2 3 4 VIH 0.5 VIL
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Reset Input No. items Symbol Min. Typ. Max. Unit Note 1 RESET_N pin Input Time twRES 10 s 1 2 RESET_N CPU access stand-by time after Negation twAW 10 ms 3 RESET_N Setup Time tsRES 0 ns 2 4 Time difference in power-on tVSKWR 1 S 3 5 Time difference in power-off tVSKWF 1 S 4 6 Power supply rise time tVRISE 200 ms Note1) The time is defined from a point where the latest VDD reached at 3.0 V and the clock to XIN pin became stable. Note2) This is a specification to the VDD that rose fastest. Note3) We recommend all the power supplies be powered on at the same time. Time difference in excess of 1 second may have an influence on reliability of the LSI. Note4) We recommend all the power supplies be powered off at the same time. Time difference in excess of 1 second may have an influence on reliability of the LSI.
6
VDD AVDD PLLVDD
3.0v 1.65v 4 6 3 1
3.0v
1
RESET_N
2 2
CS_N XIN
5
VDD AVDD PLLVDD
3.0v
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CPU Interface Parallel Interface No. Items Symbol Min. Typ. Max. Unit Note 1 PS2-0: setup time tsA 4 1 2 PS2-0: hold time thA 0 1 3 CS_N: setup time tsCS 0 2 4 CS_N: hold time thCS 0 2 5 D7-0: output data turn on time tonD 0 6 D7-0: output data turn off time toffD 10 7 D7-0: output data valid delay time tdD 0 8 D7-0: output data hold time thD 0 ns 9 WAIT_N,READY_N: turn on time tonWAIT 0 10 WAIT_N,READY_N: valid delay time tdWAIT 13 11 WAIT_N,READY_N: turn off time toffWAIT 10 12 D7-0: input data setup time tsD tSYCLK+10 13 D7-0: input data hold time thD 0 14 READY_N: hold time thREADY 0 15 command pulse active time taCMD 2tSYCLK 3 16 command pulse inhibit time tiCMD 4tSYCLK 3 17 command cycle time tcCMD 6tSYCLK 3 Note1) Regulations for WR_N, RD_N signal. However, in CS_N control, these regulations are for CS_N. Note2) Conditions to be the control for WR_N, RD_N control. if it does not meet the regulation, the control turns into the CS_N control. Note3) The command pulse means a low active pulse, which is made by the OR operation performed between each of WR_N and RD_N signal and CS_N signal. CPU Read Cycle
PS2-0
1 2
CS_N
3 4
RD_N
8 5
6
D7-0 WAIT_N
High-z 10 9 High-z 7 9 14 11 7 11
High-z
High-z
READY_N
High-z
High-z
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CPU Write Cycle
PS2-0
1 2
CS_N
3 4
WR_N
12 13
D7-0
11 9
WAIT_N
High-z 10 9 14 11
High-z
READY_N
High-z
High-z
Access Cycle
CS_N WR_N RD_N
15 17 16 15 17 16 15 17 16 15 17 16
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Serial Interface No. Items 1 SCLK Clock Cycle Time 2 SCLK Clock High Level Pulse Width 3 SCLK Clock Low Level Pulse Width 4 SCS_N: setup time 5 SCS_N: hold time 6 SDIN: setup time 7 SDIN: hold time 8 SDOUT: output data delay time 9 SDOUT: turn off time 10 SCS_N:pulse inhibit time Symbol twSCLK twhSCLK twlSCLK tsSCS thSCS tsSDI thSDI tdSDO toffSDO tiSCS Min. 400 200 200 50 50 50 50 Typ. Max. Unit Note
ns 100 20 400
SCS_N
4 1 3 2 5
SCLK
6 7
SDIN
8 9
SDOUT
Hi-Z
10
SCS_N
SCLK
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Pattern Memory Interface No. Items 1 MA24-0 : output delay time from SYCLK 2 MOE_N : output delay time from SYCLK 3 MWE_N : output delay time from SYCLK 4 MD15-0 : input setup time to SYCLK 5 MD15-0 : input hold time from SYCLK 6 MD15-0 : output delay time from SYCLK 7 MA24-0 : hold time from MOE_N 8 MD15-0 : input hold time from MOE_N, MA 9 MA24-0 : hold time from MWE_N 10 MD15-0 : hold time from MWE_N 11 MD15-0 : turn off time from MWE_N 12 Output turn off/on time from /RAHZ Note1) SYCLK is an internal clock. Symbol tdMA tdOE tdWE tsMD thMD tdMD thMAR thMDI thMAW thMDO toffMDO ton/offRA Min. 2 2 4 0 0 0 1 1 1 Typ. Max. 16 11 11 Unit Note 1 1 1 1 1 1 ns
24
6 25
Memory Access Cycle (Random Read Cycle)
SYCLK MA24-0
1
1
2
2
7
MOE_N
3 8 4 5
MWE_N MD15-0
Memory Access Cycle (Write Cycle)
SYCLK MA24-0 MOE_N
1
1
2
9 3 3
MWE_N
6
11 10
MD15-0
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RAHZ_N
MA[24:0], MD[15:0], MCE_N, MOE_N,MWE_N RAHZ_N
12 12
The AC characteristics of the external memory, which connects to the VC1 must meet the following conditions. (The following conditions are the value, which are converted from the AC characteristics, and does not guarantee the following specification directly. And, the following name of the items is for the external memory connected. And, the following item names are mainly for the external memory connected.) F in the following formula means the number of the Floating Clock that is set by R#23:FLTIM[1:0], and R means the number of the Random Access Clock that is set by R#24:RDM[3:0], and P means the number of the Page Mode Access Clock that is set by R#24:PAG[2:0]. Therefore, if a condition does not meet the following condition, set so that the register meets the following conditions. No. 13 14 15 16 17 18 Items Address, Access Time Output Enable Time Page Mode Access Time Data Turn On Time Data Turn Off Time Data Setup Time Conditions It should be (F + R) * tSYCLK - tdMA(max) - tsMD(max) or lower. It should be R * tSYCLK - tdOE(max) - tsMD(max) or lower. It should be P * tSYCLK - tdMA(max) - tsMD(max) or lower. It should be 0[ns] or over It should be F * tSYCLK - tdOE(max) + tdWE(min) or lower. It should be R * tSYCLK - tdMD(max) + tdWE(min) or lower.
MA24-n MA(n-1)-0
13 15 7
MOE_N
9 14 17
MWE_N
18 10 16 8 8
MD15-0
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4GV629A50
YGV629
Display Timing Signals No. Items 1 DOTCLK: delay time VSYNC_N,HCSYNC_N,BLANK_N,DR5-0,DG5-0, 2 DB5-0, YS_N : output hold time VSYNC_N,HCSYNC_N,BLANK_N,DR5-0,DG5-0, 3 DB5-0, YS_N : output delay time 4 FSC: delay time 5 HSIN_N, VSIN_N: input setup time 6 HSIN_N, VSIN_N: input hold time Symbol tdDOTC thDISP tdDISP tdFSC tsSIN thSIN 10 0 Min. 0 10 20 Typ. Max. 20 Unit ns ns ns ns ns ns
DTCKIN or XIN
1 1 1
DOTCLK
3 2
Outputs
5 6 valid
Inputs
XIN
4
FSC
-23-
4GV629A50
YGV629
Analog Characteristics
RGB pin Output Characteristics
Items Resolution Settling Time
Output Propagation Delay Time
Conditions
Min.
Typ.
Max. 6 20
Output Voltage Amplitude (Vp-p) RL = 37.5 CL = 30 pF Maximum Output Voltage IREF = -9.38mA (VWHITE) Minimum Output Voltage (VBLACK) Vp-p Deflection of R,G,B
0 0.7 0.7 0 3
Unit bit ns ns V V V %
Settling time is defined as the interval between the point at which DAC output level comes up to 50% and the point at which the output level reaches and stays within 1/2 LSB centered on the resulting output level. Output Propagation Delay Time is defined as the interval between the rising edge of DOTCLK and the point at which DAC output level comes up to 50%.
DOTCLK
1/2 LSB R G B 1/2 LSB
Output Propagation Delay Time
50 %
Settling Time
Measurement Circuit R,G,B
RL
CL
-24-
4GV629A50
YGV629
Package Outline Drawing
-25-
4GV629A50
YGV629

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